1. Field of the Invention
The present invention relates to an information processing apparatus and an information processing method and, more particularly, to a memory access method for an information processing apparatus.
2. Description of the Related Art
A DRAM is currently used as a main memory for various kinds of devices. A DRAM device is formed by a plurality of banks, each of which is formed by a plurality of pages. The DRAM has a high-speed access mode called a page mode, which allows access in a short time without precharge (a page close) during access (a page hit) to one page within a bank of the DRAM. To access another page within the same bank (a page miss), however, it is necessary to close, by precharge, the page for which a write or read operation has been executed, and to open the other page by designating a new ROW address, thereby accessing the other page.
To deal with this, there has been disclosed a technique of increasing the memory access speed by controlling a precharge operation (a page close) according to the memory access pattern of each processing apparatus. For example, according to a method described in Japanese Patent Laid-Open No. 2004-295322, a bus master notifies a memory controller of an address to be accessed next in addition to an address to which access is currently requested. According to this notification, the memory controller determines whether to perform a precharge operation (auto-precharge operation) after accessing the requested address. According to a method described in Japanese Patent Laid-Open No. 5-210569, a bus master compares a current address with a prefetch address. The bus master then uses a dedicated signal line for indicating a page hit/page miss to notify a memory controller of whether it is necessary to perform an auto-precharge operation.
According to the method described in Japanese Patent Laid-Open No. 2004-295322, however, the memory controller needs to buffer an address to be accessed later, thereby increasing its circuit scale. This may also increase the cost. On the other hand, according to the method described in Japanese Patent Laid-Open No. 5-210569, the bus master uses the dedicated signal line for indicating a page hit/page miss to notify the memory controller of whether to perform an auto-precharge operation, thereby increasing the number of wiring lines. Furthermore, to add such a signal line, it is necessary to change a bus interface. These points may also increase the cost.